Acceleration Robotics partners with PlanV for an open source RISC-V microcontroller for robotics

Acceleration Robotics partners with PlanV for an open source RISC-V microcontroller for robotics

Performance-enhancing company Acceleration Robotics has announced a partnership with Germany’s PlanV, which will see the pair build a microcontroller specifically for their Robotic OS (ROS) 2 projects, using the free and open source RISC-V architecture as a foundation.

Although microcontrollers are generally accepted as specialized programmable devices, most microcontrollers [Microcontroller Units] Acceleration Robotics founder Victor Mayoral-Felch explains the problem companies are looking to solve, which is used in robotics today, “There aren’t many proprietary robots in any of them.”

“Most robotics today use ROS 2,” continues Mayoral-Vilches, “and the ways to enable this in microcontrollers are often complex and difficult to optimize for latency and real time. Our goal is to design open source hardware and MCUs that have the capabilities of embedded bots and we will That’s by building on open standards such as ROS 2 and RISC-V.”

“The single most interesting feature of RISC-V ISA and related open source applications is the ability to build extensions and customizations,” PlanV founder Massimiliano Giacometti adds about the decision to build around RISC-V. “The growing field of hardware-accelerated robotics is the perfect playground to test and demonstrate the capabilities, flexibility, and maturity of these technologies.”

This partnership marks the first time Acceleration Robotics has switched to hardware dedicated to boosting ROS 2: earlier this year The company launched Robotcorean undefined hardware acceleration framework capable of running on CPUs, GPUs, and FPGAs and delivering up to 500 times the performance depending on the specific hardware and workload.

Dubbed roscore-v, the microcontroller will use a 32-bit implementation of RISC-V as a single-core, four-stage pipeline chip with 512 KB of persistent SRAM, general purpose input/output (GPIO) including This includes four PWM channels, two UART, two I2C buses with an additional client, two QSPI buses, an SDIO bus, a fast Ethernet connection, and support for Object Management Set Data Distribution Service (DDS) and real-time subscription and publishing protocol interoperability standards ( RTPS).

The companies claim that the design, which will be released under permitted Apache 2.0 and MIT licenses, is “silicon-stitched” on nodes ranging from low-cost 130nm to low-power 22nm. The chip is also claimed to be designed with energy efficiency in mind with a power envelope measured in milliwatts, but neither company has released official benchmark results to support the claim.

Companies are developing the chip as part of ROS 2 hardware acceleration working group, the design is initially installed on an FPGA before silicon output for possible mass production. For this, however, no deadline has been set yet.

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